DSP-based USB interface design

1 Introduction

The data processed by the DSP is often transmitted to the PC for storage and reprocessing, so the high-speed communication problem between the DSP and the PC must be solved. This design scheme uses Texas Instruments' C5000 series DSP chip TMS320VC5416 as the microprocessor. It uses the USB2.0 interface chip CY7C68001 provided by Cypress to realize the USB2.0 slave interface design, so that the PC and DSP pass USB2. The 0 interface enables high-speed bidirectional transmission of data.

2 TMS320VC5416 and CY7C68001 EZUSBSX2 hardware interface design

The system solution uses a PC as the host computer, which is responsible for detecting the device access and enumerating and identifying on the USB bus, and can control the data transmission by running an application on the PC. The USB chip acts as a USB device end and connects the data exchange between the DSP and the host computer. DSP is used to implement USB protocol. DSP data is used to realize DSP data communication with PC through USB interface, and the descriptor writing of USB chip and the processing of various command states are realized by DSP programming.

The TMS320VC5416 is a 16bit fixed-point high-performance DSP from TI. Due to its low power consumption and high performance, the VC5416's separate instruction and data space allows the chip to have high parallel operation capability, allowing simultaneous access of instructions and data in a single cycle. In addition, the highly optimized instruction set makes the chip highly computationally fast, and the chip itself has a wide range of on-chip memory resources and a variety of on-chip peripherals, so it has been widely used in the engineering community.

Cypress's CY7C68001 EZ-USB SX2 is a high-performance, easy-to-use USB 2.0 interface chip that satisfies the USB 2.0 protocol and works in high-speed (480Mbps) or full-speed (12Mbps) mode, providing a control endpoint for Requests for handling USB devices and four configurable endpoints for transport control and data signals. These four endpoints share a 4KB FIFO space with a standard 8-bit or 16-bit external host interface for seamless connection to multiple standard micro Processors, such as DSP, ASIC, and FPGA, can be set to synchronous or asynchronous interfaces according to requirements, and integrated on-chip phase-locked loop (PLL). The chip is widely used in DSL modems, MP3 players, card readers, and digital cameras. , scanners, printers and other equipment.

The hardware interface design of the system is shown in Figure 1 and Figure 2. The two communicate through the data, address bus, and read and write signal lines. The chip select signal of CY7C68001 is connected to the I/O space chip select signal of TMS320VC5416, CY7C68001. The FIFO is extended on the I/O space of the VC5416.

The power supply part uses a 1117 to convert 5V to 3.3V to supply CY7C68001EZ-USB SX2. The magnetic ground is connected between the analog ground and the digital ground. The reset part adopts the RC circuit design, and the typical data is 100KΩ and 0.1μF.

3 interface operation principle

The CY7C68001 has two external interfaces:

(1) Command interface: used to access the CY7C68001 register, Endpoint 0 buffer, and description table.

(2) FIFO data interface: used to access data in four 1K byte FIFOs.

Both external interfaces can be accessed synchronously or asynchronously.

This design is accessed asynchronously. According to the address allocation of Figure 3, the three high-order address lines (A11, A12, A13) of TMS320VC5416 are used to connect FIFOAD0/1/2 of CY7C68001 to select FIFO2, FIFO4, FIFO6, FIFO8 and command interface. The address table is shown in Figure 3. Shown. When the address line FIFOADR[2:0] of CY7C68001 is 100B, the command port (Command) of CY7C68001 is selected. Through the command port of CY7C68001, you can access 37 registers, Endpoint 0 buffer (64 byte FIFO) and description table (500 bytes FIFO). The read and write modes of these registers are secondary addressing mode. First, the subaddress and operation type (read or write) of the register to be addressed are written through the command port, and then the data is read or written to the corresponding register through the command port.

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