Tuojiang wearable layout domestic low-power FPGA exhibition Xiongwei

On January 16th, at the “ 2015 IoT Technology and Application Innovation Conference ” hosted by Electronic Enthusiasts , Wang Haili, vice president of local FPGA manufacturer Jingwei Yage, gave a keynote speech on “ Home-made FPGA Chips Helping Fast Innovation of Wearable Devices Applications ”. .

In the past year and a half, we have seen a large number of wearable devices released, all of which promise to change our way of life. From smart watches to smart glasses, a smart device product development competition is taking place. Developers and designers are also gearing up and determined to make their own designs. The domestic FPGA chip maker Jingwei Yage is one of the representatives, carrying its own unique design plan to get a slice of this huge wearable market.

Wang Haili, vice president of Jingwei Yage, pointed out that the cost and power consumption of FPGAs have undergone tremendous changes and can be directly put into mass production.

As a wrist-type device with a large sales volume in wearable devices, the solutions adopted by the manufacturers are mainly based on the mode of “MCU/AP+sensor+communication module”. So why is the solution provider not using FPGA? Wang Haili, vice president of Jingwei Yage, explained: “Usually FPGAs give the impression of high power consumption and large size.” This is obviously not suitable for small wearable devices. Wang Haili continues to add: "The current FPGA cost and power consumption have undergone tremendous changes and can be directly put into mass production." For example, Samsung's smartphones already use low-power FPGAs .

Market bottlenecks, where are the opportunities for FPGAs?

At present, there are still some bottlenecks in the development of mobile and wearable devices: AP chips are difficult to meet the increasing demand for the number and types of sensors in the market; the market puts higher demands on product differentiation design; function increase and performance enhancement will lead to power consumption. Keep growing. Under the bottleneck, where is the opportunity for FPGA?

FPGA opportunity

FPGA as coprocessor: interrupt handling

Multi-touch will generate a large number of interrupts to the application processor at the same time, and the generation of a large number of interrupts will affect the performance of the processor. Low-power FPGAs can solve this problem well: store and manage multiple interrupts at the same time, and transfer interrupts to the processor according to priority to reduce the burden on the processor.

FPGA is responsible for sensor management: "auto polling" sensor

Ordinary sensors require the processor to constantly query its state, so that the processor needs to be on standby and unable to enter sleep mode, thus increasing power consumption. Real-time queries for such sensors can be achieved with ultra-low-power FPGAs, while data can be filtered and processed, and interrupts can be notified to the processor to read data only when necessary.

FPGA is responsible for interface extension: SPI interface extension

When multiple peripherals need to communicate with the application processor through the SPI interface, the rate cannot meet the requirements. How to solve it? The ultra low power FPGA interface is converted to a high speed parallel interface to communicate with the processor. Moreover, when the system requires two SIM cards, it can be considered to be controlled by two baseband processors, and communication between the two processors can be realized by an ultra-low power FPGA.

It can be seen that in the era of fierce market competition and application innovation, small-sized, micro-power, low-cost FPGA products will provide incredible functions for smartphones and wearable devices!

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