Power-supply DC-DC converter technology based on NCP1031 design - Power Supply Circuits - Circuits
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PoE background introduction
As the IEEE802.3AF standard, it has become a reality to feed Ethernet communication devices through Ethernet data transmission lines as long as the terminal power requirement is less than 13W. Details of DC power transmission and related terms can be found in the IEEE document. A PoE consists of two power entities, a Power Supply Device (PSE) and a Powered Device (PD). The PSE typically provides a nominal 48V DC voltage to the LAN cable, while the PD is a small DC/DC converter at the other end of the cable that converts 48V to a logic level such as 5.0Vdc or 3.3Vdc for communication circuitry. The PD should be capable of operating at a maximum average input power of 12.95W and can withstand input voltages in the 36 to 57Vdc range. There is also a need for a specific "protocol" to implement PD detection (signature mode) and classification based on maximum power level (classification mode).
Signature Detection: The upstream PSE device detects the PD by delivering two different voltages in the range of 2.8 to 10 Vdc to the PD input. A PD device is considered to exist if the PD impedance measured by the V/I slope is greater than 23.7 kΩ and less than 26.25 kΩ. If the impedance is less than 15kΩ or greater than 33kΩ, the PD is considered to be absent and no further voltage is applied.
Classification mode: In order to classify the PD according to the target power level, the PSE also delivers a voltage between 14.5 and 20.5 Vdc to the PD. The type of PD is determined based on the absorption current of the PD at this voltage, and is summarized in the following table.
Additional input characteristics
In addition to the signature and classification circuitry, the PD must also include circuitry that limits the inrush current from the PSE to 400mA when the input voltage arrives, and prevents any quiescent current or impedance caused by the DC/DC converter during the signature and classification process. Was ignored.
Specific signature/classification circuit
Referring to the schematic shown in Figure 1, the input signature and classification circuit is designed around several discrete and low-cost ON Semiconductor devices, including the TL431 programmable reference circuit, 2N7002 signal-level MOSFET, 2N5550 NPN transistor, and NTD12N10. MOSFET and several Zener diodes and resistors and capacitors. To achieve signature detection, the 24.9k resistor (R1) is placed directly at the input. It should be noted that during the signature detection phase, the input voltage is below 10V, and the constant current source consisting of U1, Q2, and R4 is off, because the breakdown of this circuit must be completed by exceeding the breakdown voltage of 9.1V. It should also be noted that the input switch MOSFET Q3, which is connected in series as a DC/DC converter loop pin, is also turned off until the input voltage exceeds approximately 27V. This voltage is equal to the sum of the breakdown voltage of D2 and the gate threshold voltage of Q3.
Figure 1: Schematic diagram of a PoE powered device (PD).
As the voltage rises to the classification level, D1 will turn on when the voltage exceeds approximately 9.8V, the current source consisting of U1, Q2, and resistor R4 is turned on, and the current is accurately determined by the U1 reference voltage (2.5V) and the classification resistor R4. Ground control.
Once the classification is complete and confirmed, the input voltage can jump to a nominal value of 48V. Once this voltage exceeds the sum of the gate threshold of Q3 and the breakdown voltage of D2, Q3 begins to conduct. However, Q3 does not suddenly turn on. Since there is an RC time constant consisting of R6 and C2, it will immediately enter the linear region. Immediate operation in the linear region limits the inrush current because Q3 is equivalent to a resistor during this time. D3 clamps the voltage at the Q3 gate to 15V, and R5 provides a discharge path for C2 when the input from the PSE is turned off. MOSFET Q1, like Q3, is also turned on at the same voltage, which turns off the U1/Q2 current source, reducing the extra leakage current from the input.
DC/DC converter working principle
The DC/DC converter is designed using ON Semiconductor's single-chip NCP1031 switching regulator chip (U2). At a maximum output power of 5.0W, the converter is configured as a discontinuous mode (DCM) flyback topology using a common TL431 and optocoupler voltage feedback mechanism. Modifying the transformer design and control loop compensation network to operate in continuous conduction retrace mode can increase the output power to 6.5W (1.3A). The input uses a differential π-type filter composed of C3, L1, and C4.
The control chip starts to start when the undervoltage terminal of pin 6 exceeds 2.5V. A resistor divider network consisting of R7, R8, and R9 sets the undervoltage and overvoltage levels of the chip to 35V and 80V, respectively. The internal startup bias is provided via pin 8 and the constant current source is driven to charge Vcc capacitor C7. Once U2 is turned on, the auxiliary winding (pins 2, 3) of transformer T1 provides a working bias through diode D1 and resistor R11.
The voltage spike caused by the leakage inductance T1 is clamped by a network of C5, D6 and R10. The actual power rating on R10 is a function of the primary to secondary leakage inductance of T1, and the lower the better. Capacitor C6 sets the switching frequency of the converter to approximately 220 kHz.
Due to the need for secondary isolation, the TL431 (U4) acts as an error amplifier and optocoupler (U3) to form a voltage detection and feedback circuit. The internal error amplifier in U2 has been disabled by grounding the voltage sense pin 3, while the amplifier output compensation node on pin 4 is used to control the pulse width through the optocoupler's photoresist. The detected output voltage is divided by R16 and R17 into a 2.5V reference level of the TL431, and the closed-loop bandwidth and phase margin suitable for DCM operation are set by C9 and R15. Additional components (C14, C15, and R12) are required to stabilize the feedback loop if configured for CCM retrace operation. The primary side of C8 provides noise decoupling and additional high frequency roll-off performance to U2. This implementation provides an output regulation that is better than 0.5% for both line and load changes, and a closed-loop phase margin better than 50°C.
The output rectifier D5 is a 3A Schottky device for efficiency, and its output voltage is filtered by a π network consisting of C11, L2, and C12. The typical peak-to-peak noise and ripple of the filtered output are less than 100mV under all normal load and line conditions. C13 provides additional high frequency noise attenuation. Typical input-to-output efficiencies are around 75% at full load (Figure 2). Higher efficiency can be achieved by replacing the D5 with a MOSFET-based synchronous rectification circuit (Ansonme's Application Note AND8127 details how to implement a simple synchronous rectification circuit for a flyback topology).
Figure 2: Diagram of efficiency versus output power.
The overcurrent protection function is provided by the internal peak current limiting circuit in the NCP1031. In a 25°C environment, when the circuit is configured for CCM retrace mode, a continuous output current of 1.3A can be provided before the overcurrent and/or overtemperature limit function is activated, and the inrush current can be as high as 1.5A. When configured in discontinuous mode, the current limit is around 1.0A and the peak current is 1.2A.
Electromagnetic design
The design of the non-continuous mode flyback transformer is shown in Figure 3. The continuous mode transformer design is shown in Figure 4. In the design of flyback transformers, the focus is on keeping the windings in a single layer and evenly distributed over the length of the window of the core structure to minimize leakage inductance. In this scenario, this can be easily achieved with Ferroxcube's small EF16 ferrite core.
Figure 3a: Description of the discontinuous mode flyback transformer.