FPGA composition, working principle and development process
1. FPGA Overview FPGA is the abbreviation of English Field Programmable Gate Array, which is a field programmable gate array. It is a product of further development based on programmable devices such as PAL, GAL and EPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. 2. FPGA chip structure The FPGA chip is mainly composed of three parts, namely, an IOE (input output element), an LAB (logic array block, a logical array block, a configurable logic block CLB for Xilinx), and an Interconnect (internal connection line). 2.1 IOE IOE is the physical interface between the chip and the external circuit. It mainly performs the driving and matching requirements of the input/output signals under different electrical characteristics, such as from the basic LVTTL/LVCMOS interface to PCI/LVDS/RSDS and even various differential interfaces. 5V is compatible with the 3.3V/2.5V/1.8V/1.5V level interface. Below is the IOE structure of ALTERA's Cyclone IV EP4CE115F29 device. IOE structure diagram of EP4CE115F29 equipment The IOEs of FPGAs are grouped into groups. Each group can independently support different I/O standards. Through flexible configuration of software, different electrical standards and IO physical characteristics can be matched, and the driving current can be adjusted. Pull-down resistors, Cyclone IV devices have 8 IO blanks (groups), see the figure below: IO Group for Cyclone IV devices
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